In system LSI of recent years, a variety of methods for achieving both high speed operation and low power consumption have been proposed and dynamic voltage control and frequency control are very effective methods.
That is, this is a method for reducing total consumption power by operating at a high frequency by raising the voltage at a high speed operation time and at a low frequency by lowering the voltage at a time when such high speed operation is not needed or for a block which does not need the high speed operation.
Although the above-described dynamic control on the voltage and frequency can be applied to a general logic circuit, it cannot be applied to a memory for a following reason, which is a problem for reduction of consumption power of an entire system.
That is, in case of SRAM (Static Random Access Memory), because static noise margin drops as the power source voltage is lowered, the voltage cannot be lowered even if the operating frequency is low.
On the other hand, in case of DRAM (Dynamic Random Access Memory), if power source voltage is lowered, the quantity of accumulated charges is reduced so that there is a possibility that no operating margin can be obtained or soft error resistance is lowered largely. Thus, the voltage cannot be lowered.
Here, recently, for example, a memory called twin transistor RAM (TTRAM: Twin-Transistor Random Access Memory) has been proposed, as disclosed in non-patent document 1.
Non-patent document 1: IEEE205 CUSTOM INTEGRATED CIRCUIT CONFERENCE pp 435-438, “A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOL”, Fukashi Morishita et al.
As indicated in the non-patent document 1, in the TTRAM, a memory cell is constituted by a structure in which a storage transistor having a storage node and an access transistor are connected in series. By changing the state of floating substrate potential of the storage transistor, memory of data is achieved and thus, a structure not requiring any capacitor for memorizing data is provided.
That is, the storage transistor uses a body region below a channel formation region as the storage node and produces a state in which a hole is accumulated (state in which the threshold voltage of the storage transistor is low) and a state in which no hole is accumulated (state in which the threshold voltage is high) to memorize data “1” and data “0” respectively.
The state in which no hole is accumulated in the storage node is produced when the storage node is lowered from high level to low level by gate coupling (capacitance coupling generated between the gate and body) and the state in which a hole is accumulated in the storage node is produced when the potential of the storage node is raised by gate coupling.